Files
document-haness/docs/virtualization/final/assets/diagrams/numa-vcpu-and-memory-placement/numa-vcpu-and-memory-placement.dot
T

16 lines
879 B
Plaintext

digraph techviz {
graph [rankdir=LR, splines=ortho, nodesep=0.55, ranksep=0.85];
node [fontname=Helvetica, fontsize=11, margin="0.18,0.12", style="rounded,filled", fillcolor=white, color="#2d4357", penwidth=1.5];
edge [fontname=Helvetica, fontsize=10, color="#364b5f", penwidth=1.4, arrowsize=0.75];
n0 [label="QEMU vCPU Thread", shape=box, style="rounded,filled"];
n1 [label="VM1 Memory Backing", shape=box, style="rounded,filled"];
n2 [label="Node 0 CPU", shape=box, style="rounded,filled"];
n3 [label="Node 0 RAM", shape=box, style="rounded,filled"];
n4 [label="Node 1 RAM", shape=box, style="rounded,filled"];
n0 -> n2 [label="vCPU Pinning", style=solid];
n1 -> n4 [label="Memory Placement", style=solid];
n2 -> n4 [label="Remote Access", style=solid];
n1 -> n3 [label="Memory Binding", style=solid];
n2 -> n3 [label="Local Access", style=solid];
}